The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
A memory controller of non-volatile memory (“NVM”) may use a variety of data encoding/decoding techniques to handle bit errors and recover data. For example, data may be encoded as one or more codewords, e.g., as low-density parity-check (“LDPC”) codewords. The memory controller may include an iterative LDPC decoder configured to decode the LDPC codewords.
Some types of codewords, such as LDPC-encoded codewords, may include an original message and associated parity data. A non-binary iterative decoder (e.g., an LDPC decoder) may process the codeword multiple times during decoding. Symbols and soft information (e.g., associated probabilities that the symbols are correct) may be passed between variable nodes and check nodes corresponding to relationships between the variable nodes. Each iteration may bring the codeword closer to the original message.
NVM may include a plurality of physical components, such as a plurality of die. If a single die fails, it may be possible to reconstruct data from the failed die using data from the other, non-failed die. However, reconstructing data on multiple die may be less successful.